Memory devices used in computing applications typically have a small number of unavoidable defects in memory cells that are created during the manufacturing process. Furthermore, defects in memory cells of memory devices can occur during the operational lifetime of the memory devices. To overcome these defects, Content Addressable Memory (CAM) schemes may be used to map the defective memory cells in a memory device such that the defects can be avoided during runtime. In a conventional Random Access Memory (RAM) device, a user supplies a memory address and the RAM device returns the data word stored at that address. In contrast, CAM is designed such that the user supplies a data word and the CAM searches the entire memory to see if that data word is stored anywhere in the memory. If the data word is found, the CAM returns a list of one or more storage addresses where the word was found (and in some architectures, it also returns the data word, or other associated pieces of data).
A defect mapping process may be used to fully test the memory device and map any defects that are found such that subsequent processes may use the memory while avoiding the defects. During defect mapping, the mapping process fully monopolizes the memory device being testing. Therefore, the defect mapping process is typically only used at the time of manufacture of the memory device before the memory device is released for use, or during some dedicated initialization step in a larger application or hardware initialization process. However, as the mapping process fully monopolizes the memory during mapping, the mapping process cannot be used during runtime as the mapping process would prevent other applications from accessing the memory device.
Additionally, data storage utilizing System-on-Chip (SoC) functionality involves many complex circuits to be run at very high speeds. Testing the functionality of these circuits with automated test equipment (ATE) and making sure that the chip runs at the target speed without any issues is very critical. To test the SoC on the ATE, a method for integrated system test (MIST) logic is implemented in the SoC. MIST logic, along with the appropriate firmware set-up can control the data path to emulate the system functionality and validate the circuits. In particular, double data rate (DDR) memory interface testing at the ATE at a maximum defined speed, commonly referred to as an at-speed test, is a major issue in all the SoCs that include the high speed DDR memory interface. Such a shortfall causes an increase in the defective parts per million (DPPM) and increased debug time, thereby leading to an increased production cost.